Job Description
· Responsible for ASIC qualification, yield improvement in engineering and ramp up phase
· Collaborate with internal R&D and external subcontractors to enhance product robustness for manufacturability
· ASIC owner and take full responsibility in mass production, e.g. yield monitor/improvement, cost down
· Perform electrical and physical failure analysis to understand failure mechanism
· Perform data mining and analysis to find root cause for any excursion and issues
· Supplier management focus on qualification and failure analysis house, wafer foundry and wafer test OSATs
· Master or Bachelor Degree in Device Physics, Electrical/Electronic Engineering or equivalent
· At least 4-6 years' experience at semiconductor foundry or fabless-IC design house as Product Engineering
· Good understanding of CMOS fab processes (logic and mixed-signal process)
· Able to do data mining and correlation analysis on process parameters and electrical test parameters
· Experience on IC failure analysis and fault localization techniques
· Knowledge/experience on ASIC test and final test is highly preferred
· Knowledge of product development, design of mixed-signal circuits is highly preferred
· Willingness to work and interact in international teams, English written and verbal must be
· Self-motivated, excellent communication skills and team spirit
· Ability to independently manage projects and subcontractors
· Package Assembly knowledge will be a plus